A Verilog dialect and source-to-source compiler, with various compile time features and macros.
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Last updated | Monday, April 29th, 2019 4:05:54pm (UTC) | ||||||
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Conflicts | None | ||||||
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Last checked | Tuesday, July 1st, 2025 6:53:27pm (UTC) | ||||||
Last edited | Monday, February 11th, 2019 9:04:41pm (UTC) | ||||||
Date added | Monday, February 11th, 2019 9:04:41pm (UTC) | ||||||
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