A Verilog dialect and source-to-source compiler, with various compile time features and macros.
|Last updated||Friday, April 19th, 2019 12:03:29pm (UTC)|
|Most recent build results|
|Last checked||Sunday, April 21st, 2019 8:03:26am (UTC)|
|Last edited||Monday, February 11th, 2019 9:04:41pm (UTC)|
|Date added||Monday, February 11th, 2019 9:04:41pm (UTC)|