rtlv

Tools for reasoning about circuits in Rosette/Racket

Build status: ok failing tests valid license

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Last updatedThursday, October 20th, 2022 12:59:27am (UTC)
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defaulthttps://github.com/anishathalye/rtlv.gitc10e4ddca3e36e2cb860859d7d69d2c90ef9b8f1
Last checkedThursday, February 9th, 2023 7:32:48am (UTC)
Last editedWednesday, October 19th, 2022 11:21:16pm (UTC)
Date addedWednesday, October 19th, 2022 11:21:16pm (UTC)
Modules
  • test/shiva/verilog/soc.rkt
  • test/shiva/verify.rkt
  • shiva/main.rkt
  • test/shiva/main.rkt