rtlv

Tools for reasoning about circuits in Rosette/Racket

Build status: ok failing tests valid license

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      Last updatedSaturday, February 1st, 2025 6:31:58pm (UTC)
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      defaulthttps://github.com/anishathalye/rtlv.git3da08dc8b3b97c8804228158687db0bbb7872259
      Last checkedTuesday, April 1st, 2025 7:38:55pm (UTC)
      Last editedWednesday, October 19th, 2022 11:21:16pm (UTC)
      Date addedWednesday, October 19th, 2022 11:21:16pm (UTC)
      Modules
      • test/shiva/verilog/soc.rkt
      • shiva/main.rkt
      • test/shiva/verify.rkt
      • test/shiva/main.rkt