rtlv

Tools for reasoning about circuits in Rosette/Racket

Build status: ok failing tests valid license

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Last updatedSunday, March 5th, 2023 2:32:38pm (UTC)
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defaulthttps://github.com/anishathalye/rtlv.gitdc7c990411ed419dc01de0650891741256f390a5
Last checkedFriday, June 14th, 2024 6:04:54pm (UTC)
Last editedWednesday, October 19th, 2022 11:21:16pm (UTC)
Date addedWednesday, October 19th, 2022 11:21:16pm (UTC)
Modules
  • test/shiva/verilog/soc.rkt
  • test/shiva/verify.rkt
  • shiva/main.rkt
  • test/shiva/main.rkt